The invention relates to integrated circuit (IC) packages and more particularly to image sensing devices and methods for fabricating the same.
An essential step in the manufacture of all integrated circuit devices is what is known as the packaging step. Packaging involves mechanical and environmental protection of a silicon chip formed at the center of the integrated circuit and provides electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
Existing package techniques for mounting a die on a substrate via the bonding points on both the die and the substrate include ball grid array (BGA), wire bonding, and flip chip. The inner traces aid in fan out the bonding points on the bottom of the substrate. The solder balls are separately planted on the bonding points to serve as an interface for electrical connection of the die to the external circuitry.
BGA packages require wiring or flip chip for mounting the die on the substrate. The inner traces in the substrate fan out the bonding points on the substrate, and electrical connection to the external circuitry is carried out by the solder balls on the bonding points. This method fails to reduce the distance of the signal transmission path but in fact increases the signal path distance, increasing signal delay and attenuation and degrading chip performance.
Thus, wafer level chip scale package (WLCSP) has received attention in recent years as a three-dimensional mounting technology as well as a new packaging technology. The WLCSP provides a small package having about the same outside dimensions as a die packaged therein. Further, WLCSP is advantageous in enabling printing of the redistribution circuit directly on the die by using the peripheral area of the die as the bonding points. This is made possible by redistributing an area array on the surface of the die, allowing the entire area of the die to be fully utilized. The bonding points are located on the redistribution circuit by forming flip chip bumps, thus, the bottom side of the die connects directly to the printed circuit board (PCB) with micro-spaced bonding points.
FIG. 1 shows a conventional integrated circuit package formed by WLCSP techniques as disclosed in U.S. Pat. No. 6,777,767, including a microlens array 100 formed on a substrate 102. Underlying the substrate 102 and sealed thereto by epoxy 104 is a packaging layer 106, typically formed of glass, along edges of which are formed electrical contacts 108, typically defining bumps 110. Conductive pads 112 connect substrate 102 to electrical contacts 108. A packaging layer 114 formed of glass and associated spacer elements 116 are sealed by means of an adhesive such as epoxy 118 and are formed over substrate 102 defining a cavity 120 between the microlens array 100 and the packaging layer 114. The packaging layer 114 is transparent and may have formed thereon a dichroic filter and/or anti-reflective coating.
In the conventional integrated circuit package illustrated in FIG. 1, however, there exists a possibility of the conductive pads 112 and the electrical contacts 108 disconnecting at a point of contact therebetween because the area of the point of contact is very small. A problem also arises in step coverage of the conductive pads 112. Additionally, coefficients of thermal expansion (CTE) of the epoxy 118, the conductive pads 112 and the electrical contacts 108 may result in mismatching and delamination, thus degrading of IC package reliability.